The present invention relates to a semiconductor memory device, and more particularly to a dynamic type semiconductor memory device employing one-transistor type memory cells.
As dynamic type memory devices, so-called one-transistor type memories which employ one transistor type memory cells each composed of one transistor and one capacitor, have been widely utilized in various fields. Such dynamic type memory devices have at least one array of memory cells in which a large number of one transistor type memory cells are arranged in a matrix form of rows and columns. A plurality of word lines are arranged in rows and a plurality of pairs of digit lines and a plurality of sense amplifiers are arranged in columns. Also, a plurality of reference cells are provided in two rows. The reference cell is composed of a transistor and a capacitor of the capacitance less than the capacitance of the capacitor of the memory cell. In practical case, a pair of reference cells are coupled to a pair of digit lines which are coupled to a pair of input terminals of a differential type sense amplifier in each of columns.
When a read operation is performed, one memory cell coupled to a selected word line produces a data signal stored therein to one of a pair of digit lines and one reference cell coupled to the other digit line of the same pair of digit lines is enabled so that the capacitor of the enabled reference cell is electrically coupled to the other digit line, in each column. The reference cell provides to the other digit line with a reference level of the binary logic levels stored in the memory cell so that the sense amplifier detects the data stored in the memory cell by comparing it with the reference level.
In general, the transistors of the memory cells and the reference cells are MOS field effect transistors and the capacitors of the memory cells and reference cells are MOS capacitors which utilize a surface portion of a semiconductor substrate as a lower electrode and a polycrystalline silicon layer formed above the opposite conductivity region via a thin layer of dielectric layer such as silicon dioxide layer. Such surface portion is usually an inversion or depletion region formed at the surface of the substrate.
Heretofore, the capacitors of the memory cells and the capacitors of the reference cells are fabricated through the same manufacturing steps and the capacitance of the capacitors of the reference cells is made smaller than that of the memory cells (e.g. one-half of the memory cell capacitor) by setting area of the capacitors of the reference cells smaller than that of the memory cells.
However, accompanied by recent increase in the memory capacity, the areas for the capacitors of the memory cells and the reference cell have become greatly reduced. As a result, deviations in areas of the capacitors of the reference cell and the memory cell have become comparatively large. Particularly, it has become difficult to keep the ratio of the areas between the capacitor of the reference cell and the capacitor of the memory cell at a designed, desired value.
The above increase in the comparative deviation in the capacitance of the reference cell capacitor with respect to the memory cell capacitor lowers operation margin in reading operations and also lowers yields of the memory devices.